(p 28)
Ch1 design methodology
As deep sub-micron semiconductor geometries shrink, traditional methods of
chip design have become increasingly difficult.
(p29)
1.1 Traditional Design Flow
1.1.1 Specification and RTL Coding
(page 32)
1.1.2 Dynamic Simulation
(page 33)
1.1.3 Constraints, Synthesis and Scan Insertion
For a long time, the HDLs were used for logic verification.
(page 34)
Synthesizing a design is an iterative process and begins with defining timing
constraints for each block of the design.
(page 35)
Usually, for small blocks of a design, DC’s internal static timing analysis is
used for reporting the timing information of the synthesized design.
Most designs today, incorporate design-for-test (DFT) logic to test their
functionality, after the chip is fabricated.
The logic and memory BIST comprises of synthesizable RTL that is based
upon controller logic and is incorporated in the design before synthesis.
The scan insertion may be performed using the test ready compile feature of
DC.
1.1.4 Formal Verification
(p36)
The main difference between formal methods and dynamic simulation is that
former technique verifies the design by proving that the structure and
functionality of two designs are logically equivalent.
(p37)
